This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In some conventional circuit designs, during write operations, a write driver may pull down a bitline too low, so that a bitcell flips logic state. To save area and power, this write driver is typically shared across multiple bitlines, and these bitlines are multiplexed together. In some cases, pass transistors are used to connect multiple different bitlines to an output of the write driver. With technology scaling, memory operating voltage is not scaled, but this logic can operate at lower voltage. To save power, a memory array can be kept at a higher core voltage, but periphery voltage can be around 250 mv less than the memory array voltage. If the pass gate of a write multiplexor (mux) is kept at periphery voltage, then at low voltage, its drive can be reduced significantly, and the write operation can become difficult to achieve. For this reason, the pass transistors can be driven by the core supply voltage, and the driver for write column select signals (yw) can be placed in a center spine (or bus) and drive all of the bitcells. For wide memory, these signals may not be limited by resistance for a long line, and due to parasitic capacitance, these signals see a low-going coupling and can act as a poor switch to discharge bitlines. As size of a data word of memory can be very wide, parasitic capacitive coupling becomes significant and highly detrimental to memory operation and function.